1. Field
The described embodiments relate to computing devices. More specifically, the described embodiments relate to a translation lookaside buffer with a hierarchy of tables for performing virtual address to physical address translations in computing devices.
2. Related Art
Many computing devices use a virtual memory technique for handling data accesses by programs being executed in a computing device. In these computing devices, when data is accessed by a program, a block of memory of a given size (e.g., 4 kB) that includes the data, called a “page” of memory, is copied from mass storage (e.g., a disk drive or semiconductor memory) to an available physical location in a main memory in the computing device. In order to avoid programs being required to manage the physical locations of the pages, a memory management unit in the computing device manages the physical locations of the pages. Instead of using addresses based on the physical locations of pages (or “physical addresses”) for accessing memory, the programs access memory using “virtual addresses” in “virtual address spaces,” which are local address spaces that are specific to corresponding programs. From a program's perspective, virtual addresses indicate the actual physical addresses (i.e., physical locations) where data is stored within the pages in memory and hence memory accesses are made by programs using the virtual addresses accordingly. However, the virtual addresses may not directly map to the physical addresses of the physical locations where data is stored. Thus, as part of managing the physical locations of pages, the memory management unit translates the virtual addresses used by the programs into the physical addresses where the data is actually located. The translated physical addresses are then used to perform the memory accesses for the programs.
To perform the above-described translations, the memory management unit uses a page table in memory that includes a set of translations from virtual addresses to physical addresses for corresponding pages in the memory. However, using the page table to translate virtual addresses to physical addresses is slow for various reasons (e.g., the size of the page table, the operations used to perform lookups for the translation, etc.). The computing device also includes a translation lookaside buffer (or “TLB”), which is a cache of virtual address to physical address translations that were previously acquired from the page table. Performing the translation from virtual address to physical address using the TLB is significantly faster than performing the translation using the page table. However, TLBs are typically limited in size due to constraints on the area that the TLB is allowed to occupy in the integrated circuits in which the TLB is fabricated. This means that the use of the TLB can be limited and some virtual address to physical address translations must still be performed using the page table.
Throughout the figures and the description, like reference numerals refer to the same figure elements.